The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 1988
Filed:
Mar. 01, 1984
Applicant:
Inventor:
Hemmige D Varadarajan, Sunnyvale, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307455 ; 307454 ; 307297 ; 323314 ;
Abstract
Three-level ECL or four-level CML are feasible when a low drop current source is incorporated in the series-gated arrangement. The low drop current source consumes less than one-tenth of the voltage span between V.sub.CC and ground. A greater portion of the voltage span between V.sub.CC and ground, up to 4 volts, is therefore reserved for the three ECL levels or four CML levels of logic. Conventional power supplies are utilized yet the number of logic functions is increased.