Circuit arrangement comprising a matrix shaped memory arrangement for

Abstract

A circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals contains known three-transistor cells having overlap write/read cycles as storing elements. The arrangement also contains a continuously steppable row selector, resettable at any time, and clock-controlled by the input data clock which comprises, respectively, two mutually phase offset signal outputs per selection step which respectively drive a write word line and a read word line which are provided per row of the matrix. The arrangement further comprises two separate bit lines, a write bit line and a read bit line per column which are respectively interconnected to all memory cells of a column, and comprises a disconnectible storage amplifier per column whose input is connected to the read bit line of the column assigned thereto and whose output is connected to the following column and serves as a data output for the assigned column. The arrangement further comprises a data input for the data signals to be delayed, the data input being connected to the write bit line of the first column and to an undelayed data output, and a reset input which is connected to the setting inputs of a first element of the row selector as well as to the reset inputs of the remaining elements of the row selector. The chronological spacing between reset pulses is selected such that it equals the required delay time which is to be set between the undelayed data output and the first delayed data output.