Erasable programmable read only memory (eprom) device and a process to

Abstract

A structure of high packing density EPROM having floating gate type FET memory cells and a fabrication process thereof are disclosed. Marginal spaces for mask alignment and bird's beak in prior art EPROM device have been cut down by applying a self alignment technique to determine both the gate length and gate width. The process for fabricating the device is disclosed. On a substrate first gate insulation film and first conductive polysilicon layer are formed. Parallel grooves for device separation are formed in a direction of gate length by photolithography. The space between the groove defines the gate width, and the width of the groove determines the spacing between the cell FETs. The groove is buried by SiO.sub.2 deposited chemical vapor deposition. The surface is etched to expose the first polysilicon layer. On this surface, a second gate insulation film and second conductive polysilicon layer are formed. The substrate is then etched leaving a parallel stripes orthogonal to the device separation grooves. The spacing of the stripe determines the device separation in the direction of gate length. Utilizing this stripes as a mask, the substrate is etched off to expose the substrate. To the exposed substrate are doped to form sources and drains. Applying the inventive process, the packing density of the memory cell has been increased by 30%.