logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4734383 B1

PDFFull Text
Date of Patent:
Mar. 29, 1988

Filed:

Nov. 22, 1985

Fabricating semiconductor devices to prevent alloy spiking

Applicant:
Inventors:

Shuji Ikeda, Koganei, JP;

Kouichi Nagasawa, Kunitachi, JP;

Makoto Motoyoshi, Fucyu, JP;

Kiyoshi Nagai, Koganei, JP;

Satoshi Meguro, Hinode, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:

Antonelli, Terry & Wands

Primary Examiner:

George T Ozaki

Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 42 ; 437 57 ;
Abstract

After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Find Patent Forward Citations

Ikeda, Shuji. (1988). Fabricating semiconductor devices to prevent alloy spiking (U.S. Patent No. 4734383). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4734383

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…