The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 1988

Filed:

May. 28, 1985
Applicant:
Inventor:

Yoshiyuki Terashima, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365206 ; 365104 ;
Abstract

A non-volatile memory circuit which may be formed on the same memory chip as a MOS integrated circuit for an electronic watch. The non-volatile memory circuit includes a power source and a high voltage application terminal for writing data. A non-volatile memory device is coupled between the power source and the high voltage application terminal. A voltage limiting circuit for limiting the voltage applied to the non-volatile memory is coupled between the power source and the high voltage application terminal. A current limiting circuit for limiting the current applied to the non-volatile memory is coupled between the high voltage application terminal and the non-volatile memory, whereby the non-volatile memory is protected from stray voltage and current writing data into the non-volatile memory. The invention may also be applied to an EEPROM arrangement in which the data may be read to or erased from the non-volatile memory without erroneous writing or erasure due to static noise or other outside noise.


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