The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 1988

Filed:

Nov. 06, 1985
Applicant:
Inventor:

Toshihisa Taniguchi, Hatano, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364900 ;
Abstract

In a multiple-block-per-entry buffer memory (BS) of the swap or store-in type, a swap-out buffer (SOB) having a capacity for at least a block is provided. On the occasion of replacing, a memory access sequence control responds to change bits and validity bits associated with an entry to be replaced as well as the block address designated for memory access so as to execute the data transfer from a main memory (MS) to BS in preference to the sweeping-out of data from BS to SOB so long as the block to be replaced need not be stored in MS. If the block to be replaced needs to be stored, the sweeping-out into SOB is executed with the utmost priority, and the data transfer from MS is then executed in preference to the sweeping-out of any other blocks to be stored into MS.


Find Patent Forward Citations

Taniguchi, Toshihisa. (1988). Swap control apparatus for hierarchical memory system (U.S. Patent No. 4733367). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4733367

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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