The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 1988
Filed:
Sep. 30, 1986
David A Van Lehn, Houston, TX (US);
Edward H Flaherty, Houston, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another. The steady-state stage is delayed, so that the noise from the initial transition does not appear at the power supply and reference supply nodes of the steady-state stage. The circuit also operates so that the output node can be put into a high-impedance state, allowing for common input/output utilization of the circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile