The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 1988

Filed:

Feb. 04, 1986
Applicant:
Inventors:

Hideto Hidaka, Itami, JP;

Kazuyasu Fujishima, Itami, JP;

Masaki Kumanoya, Itami, JP;

Hideshi Miyatake, Itami, JP;

Katsumi Dosaka, Itami, JP;

Tsutomu Yoshihara, Itami, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 38 ; 371 21 ; 324 / ;
Abstract

A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.


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Hidaka, Hideto. (1988). Semiconductor memory device (U.S. Patent No. 4730320). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4730320

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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