Static semiconductor memory device

Abstract

A memory cell array consists of a plurality of memory sections. A pair of bit lines are provided for each column, and word lines are provided each for each row in each memory section. One end of the current path of a first transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. One end of the current path of a second transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. The current capacity of the first transistor is larger than that of the second transistor. After an address signal varies and a predetermined period elapses, the first transistor in the selected section turns on, the second transistor in the selected section turns off, the first transistor in the nonselected section turns off, and the second transistors in the nonselected section turns on. The bit lines in the selected section are charged for a predetermined period of time after the address signal changes, to pull up the voltages of the bit lines in the nonselected section to a power supply voltage. A row decoder renders the word line active in level after the first transistor connected to the bit lines of the selected section is turned off according to an address signal.