The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 1988

Filed:

Dec. 16, 1985
Applicant:
Inventor:

James J Stipanuk, Chandler, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
365189 ; 365230 ; 365179 ;
Abstract

A circuit for selecting a row of memory cells of an array is disclosed that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and utilizes the capacitive charge on the lower word line in the selection of the row. The array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between bases of active load transistors in each of the memory cells in a row and the word line of that row for selecting that row of memory cells.


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