The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 1988
Filed:
Jul. 22, 1986
Tsuneo Kinoshita, Kokobunji, JP;
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Abstract
A logic circuit on a substrate is switchable between a test mode and an operational mode. First and second NOR gates are cross-coupled and may be switched between an operational mode and a test mode by the application of a control signal to first and second transfer gates coupled to the inputs of the NOR gates. The first NOR gate includes a p-type region and an n-type region formed in said substrate and traversed with first and second conductive layers insulated from the p and n-type regions. Thus, the first NOR gate includes two p-channel transistors and two n-channel transistors. The second NOR gate is also formed by a p-type region and an n-type region traversed with third and fourth conductive layers. Thus, the second NOR gate also includes two p-channel transistors and two n-channel transistors. The transfer gates are located on the substrate between the first and second NOR gates. Both transfer gates include an n-type region formed in the substrate with a conductive layer disposed over the n-type region. In the operational mode, the cross-coupled NOR gates may perform as a flip-flop. In the test mode, each NOR gate essentially becomes an inverter.