The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 1988

Filed:

Mar. 30, 1987
Applicant:
Inventors:

Yefim Bukhman, Tempe, AZ (US);

Carroll M Casteel, Mesa, AZ (US);

Gary F Witting, Mesa, AZ (US);

Assignee:

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 33 ; 437 67 ; 437241 ;
Abstract

A process is described for producing semiconductor devices using a single master mask which determines the lateral dimensions of certain critical device and/or device contact regions in combination with a surrounding isolation wall. Various dielectric layers and isotropic and anisotropic etching steps are utilized in combination with a series of block-out masks to permit etching of a trench in the location of the peripheral isolation wall image in the master mask which is subsequently filled with a dielectric-semiconductor combination. For the case of a vertical bipolar transistor, a base region is implanted using an oversize selector mask. Successive block-out masks are then used to select the particular openings in the master mask which will form the base contact, the emitter and emitter contact and the collector contact. No precision alignments are required between the master mask and the selector or block-out masks. The described method is well suited to the production of transistors, in VLSI applications having minimum lateral dimensions in the micron to submicron range.


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