The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1988
Filed:
Jul. 30, 1986
Robin W Cheung, Cupertino, CA (US);
Hugo W Chan, Fremont, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An improved process for fabricating a static RAM cell having a polysilicon load resistance is provided. Following formation of source, gate and drain regions, a planarized dielectric structure is formed over the junction regions, and via openings which expose portions of the source and drain regions are created. The via openings are filled with polysilicon interconnects, appropriately doped for low resistance contacts. Where the contact includes a resistor load, the polysilicon is not doped. Thus, the prior art approach of providing doped and undoped regions along the same polysilicon interconnect is not employed. Rather, the doped and undoped regions are physically separated. Consequently, the minimum length of the poly load is limited only by the ability to form via openings of small dimensions.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile