Apparatus for out-of-order program execution

Abstract

A first load vector instruction signal V1 is read from an instruction buffer into an instruction read register. V1 is decoded and routed simultaneously to scalar and vector processor instruction issue registers. V1 is next routed to a vector instruction stage register and from there to a vector load execution pipe. A second load vector instruction signal V2 proceeds in a similar manner until it reaches the vector instruction stage register and is held there because the vector load execution pipe is busy with V1. A store vector instruction signal S1 proceeds in a similar manner until it reaches the vector processor instruction issue register. S1 cannot proceed further as V2 is queued in the vector instruction stage register. A bypass mechanism includes a bypass test register, a bypassed instruction hold register and a bypass control and sequence logic. S1 is transferred into the bypass test register at each clock cycle. The bypass control and sequence logic initiates a bypass sequence. Under the control of the bypass control and sequence logic, V2 is transferred from the vector instruction stage register to the bypassed instruction hold register. S1 is allowed to proceed to the vector instruction stage register and then on to a vector store execution pipe. V2 is returned to the vector instruction stage register completing the bypass sequence.