The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 1988

Filed:

Mar. 31, 1986
Applicant:
Inventor:

Martin W Redfern, Maidstone, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330263 ; 315403 ;
Abstract

A linear high power amplifier suitable for low voltage operation comprising a push-pull output stage (Q1, Q2) arranged to control the voltage supplied to a load (Z.sub.L) in dependence on an input signal (V.sub.IN) applied to the amplifier. Means (L.sub.S, S) is provided for separately supplying to said load (.sub.Z L) a current (I.sub.S) which changes at a rate faster than the maximum rate of change of current (I.sub.L) in the load (Z.sub.L) required by the input signal (V.sub.IN) thereby to produce a corresponding change in the current (I.sub.A) required to be supplied by the output stage (Q1, Q2) to the load (Z.sub.L) in order to maintain the voltage across the load (Z.sub.L) at the value required by said input signal (V.sub.IN). Switching means (Q3, Q4, C) operated in dependence on the value of the current (I.sub.A) supplied to the load (Z.sub.L) by the output stage (Q1, Q2) causes the sense in which said changing current (I.sub.S) changes to reverse when said current (I.sub.A) supplied by said output stage (Q1, Q2) exceeds a predetermined positive value (I.sub.AP) or a predetermined negative value (I.sub.AN) which predetermined values are less than the total current (I.sub.L) required by the input signal (V.sub.IN) to be supplied to the load (Z.sub.L), thereby to restrict the current (I.sub.A) supplied to the load (Z.sub.L) by the output stage (Q1, Q2) to values between said predetermined values (I.sub.AP, I.sub.AN).


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