Cmos logic circuit

Abstract

A monodirectional logic form is provided using a bistable circuit of the set-rest type comprised of two cMOS inverters connected in parallel to a source of power (V.sub.dd) by a power-down p-channel MOS transistor. Each of the cMOS inverters is comprised of a first p-channel MOS transistor in source-drain-drain-source series with an n-channel MOS transistor. Two signal-pass n-channel MOS transistors are provided, one a signal-pass transistor connected as a series switch in a first signal (d) line to the input terminal of one cMOS inverter and the output terminal of the other cMOS inverter, and the other a signal-pass transistor connected as a series switch in a second complement signal (d) line to the input terminal of the other cMOS inverter and the output terminal of the one cMOS inverter. The cMOS inverters are thus directly cross-coupled, input to output, and the input to each is gated by one of the pass transistors, while a first phase of a nonoverlapping two-phase clock signal source is applied to the gates of the power-down and signal-pass transistors. A set-reset circuit coupled in series, either directly or by switching functions is connected to receive the second phase clock signal. The signal pass transistors are connected to mutually exclusive switching functions (series-parallel nMOS network) that provide current paths to circuit ground in response to data signals, or circuit paths to the output terminals of another set-reset circuit.