The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 1987
Filed:
Apr. 25, 1985
William H Davenport, Hillsboro, OR (US);
Gary D McCormack, Beaverton, OR (US);
George S LaRue, Beaverton, OR (US);
TriQuint, Beaverton, OR (US);
Abstract
An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure. The output stage also comprises a controllable current source connected between the source of the depletion-mode FET and the drain of the second enhancement mode FET structure, for providing drain current to the second enhancement mode FET structure when the potential of the drain of the first enhancement mode FET structure exceeds a predetermined level, and depriving the second enhancement mode FET structure of drain current when the drain of the first enhancement mode FET structure is below the predetermined potential level.