The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 1987
Filed:
Jul. 21, 1986
Kenneth R Haddad, Schaumburg, IL (US);
Richard J Vilmur, Palatine, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Improved speakerphones (120 and 130 in FIG. 1) for both radio (112) and landline (138) telephones are described. The improved speakerphones (120 and 130) each include a microphone (102 and 132), a speaker (104 and 134) and unique control circuitry (106 and 136). The control circuitry of the improved speakerphone (200 in FIG. 2) interfaces a microphone (250) to a transmit signal (220) and speaker (260) to a receive signal (222) of a duplex communication path, such as a radio channel or telephone line. Variable gain stages (212 and 202) amplify and attenuate the speaker and microphone audio paths, respectively, in response to a gain control signal (223) from control logic (230). Transmit and receive signal detectors (206 and 207), each include gain adjust circuitry (208) a logarithmic amplifier (240), an envelope detector (241), a smoothing filter (245), a valley detector (242), a summer (243) and a comparator (244) for detecting the presence of audio signals in environments that may be subject to high background noise. Binary output signals from the transmit and receive signal detectors (206 and 207) are applied to control logic (230) which generates the gain control signal (223) and detector control signal (224). The control logic (230) includes delay circuitry (316 and 318) and gain control circuitry (392) for generating the gain control signal (223), the magnitude of which varies the amount of gain stages (202 and 212). Delay circuitry (316 and 318) and logic circuitry (304, 306, 308, 310, 312 and 314) in control logic (230) set and reset a flip-flop (302) for generating the detector control signals (224 and 225). Detector control signals (224 and 225) are coupled to gain adjust circuitry (208) and smoothing filter (245) for adjusting gain and response time of transmit and receive signal detectors (206 and 207).