The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 1987

Filed:

Apr. 12, 1985
Applicant:
Inventors:

John W Bailey, Berkshire, GB;

Paul A Hayter, Berkshire, GB;

Brian R Mason, Berkshire, GB;

Graham N Turner, Berkshire, GB;

Assignee:

Mars, Inc., McLean, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ;
U.S. Cl.
CPC ...
324 / ; 324 / ; 3241 / ;
Abstract

An in-circuit testing apparatus (manufacturing defects analyzer) for the determination of manufacturing defects in an electrical circuit board such as short circuits, tracking faults, mininserted omitted and out-of tolerance components etc., and not for effecting full functional testing of the circuit board, comprises an array of bidirectionally current conducting analog switching networks each of which defines a test point for connection to a node of a circuit board and connectable, under software control of the respective switchng network, either to a stimulus source or to a reference (e.g. ground) potential and simultaneously also to an input of a measurement facility. A resistor, capacitor, inductor or other circuit component can be connected between the test points defined by two of the switching networks and can thus be subjected to an appropriate stimulus and its response measured and analyzed for determining the viability of the respective component. A modified form of the apparatus enables the gain of discrete transistors also to be monitored. A desk-top form of the apparatus has a recess in its main housing for receiving an interchangeable board-probing module which is customized to a particular board to be tested and has a customized probe array coupled to one part of a universal interface connector, the other part of the universal interface connector being provided in the recess in the main housing such that the two parts come together when the module is inserted into the housing recess.


Find Patent Forward Citations

Bailey, John. (1987). Printed circuit board fault location system (U.S. Patent No. 4714875). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4714875

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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