Stability testing of semiconductor memories

Abstract

Design/test technique to facilitate improved long-term stability testing of static memory arrays with high inherent data retention characteristics at extremely small standby current requirements. The test concept is based on the fact that defects in the standby condition system of a memory array have a bearing on the word line standby potential. Detection of word line potentials differing from their nominal value defined for the standby state, i.e., in the unselected operation mode, is accomplished by performing a disturb write operation into the partly or totally unselected array. As a result cells along a defective word line are less disturbed than those along a goood or normal word line. This inverted error pattern is used for screening defect word lines which otherwise would show up as long-term data retention problems.