The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1987
Filed:
Nov. 13, 1986
Applicant:
Inventors:
Tatsuo Otsuki, Takatsuki, JP;
Akio Shimano, Osaka, JP;
Hiromitsu Aoki, Takatsuki, JP;
Ikuko Aoki, Takatsuki, JP;
Assignee:
Matsushita Electric Industrial Co., Ltd., Kadoma, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307450 ; 307448 ; 307443 ; 307475 ;
Abstract
A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (V.sub.I); and thereby a high load drivability with a low power consumption rate is realized.
Quick Actions:
Otsuki, Tatsuo. (1987). Buffered fet logic gate using depletion-mode mesfet's. (U.S. Patent No. 4712023). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4712023
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile