The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 1987
Filed:
Feb. 03, 1986
Kazumi Hatayama, Hitachi, JP;
Terumine Hayashi, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Disclosed is a method of level sensitive testing of a logic array system and an LSI chip having testing means incorporated therein. The present invention is especially suitable for testing a RAM and the function of a logic unit which is a functional peripheral of the RAM. The LSI chip comprises means for selecting a specific address of the RAM, means for writing a signal at the specific address of the RAM and reading out the data from the specific address of the RAM, and means for selecting the operation of the chip between a usual operation mode and a scan-in/scan-out diagnostic mode for testing the RAM or functional peripheral of the RAM. Testing can be easily conducted by addition of a small number of logic elements. The larger the number of address signal lines and the number of data signal lines of the RAM, the more effective the testing method becomes.