Method of producing semiconductor integrated circuit having parasitic

Abstract

A complementary MOS type integrated circuit is produced by a method which comprises the steps of: disposing a first mask material layer on the surface of a semiconductor substrate, the first mask material layer having a first impurity introducing region corresponding to a desired well forming pattern; forming a well region by selectively doping an impurity into the surface of the substrate through the first impurity introducing region; forming a second mask material layer in such a manner as to cover both the first impurity introducing region and the first mask material layer; disposing first and second mask layers on the second mask material layer, the first and second mask layers respectively corresponding to a first active region pattern within the well region and a second active region pattern outside the well region, thereby defining a second impurity introducing region corresponding to a desired parasitic channel stopper pattern between the stack portion of the first and second mask material layers and the first mask layer; selectively ion-implanting an impurity into the surface of the well region through the second impurity introducing region; selectively removing the first and second mask material layers by selective etching using the first and second mask layers; and selectively thermally oxidizing the surface of the substrate using the remaining portions of the first and second mask material layers as a mask, thereby simultaneously forming a field oxide film and a parasitic channel stopper region containing the implanted impurity. According to this method, the parasitic channel stopper region is self-aligned with both the well region and the field oxide film.