Mos read-only memory systems

Abstract

A MOS ROM system is arranged such that during a readout operation a current flows from at least one data line selected from among a plurality of data lines. The read and sense circuit detects a memory state of a selected memory cell based on the amount of inflow current. A non-selected memory cell does not contribute to a word line load capacitance, and the word line load capacitance upon switching word lines can be reduced. A signal transfer rate can therefore be increased, and a data read rate can thereby be speeded up. Moreover, a read and sense circuit for a ROM is adapted such that first and third MOS transistors and a first current supply circuit, and second and fourth MOS transistors and a second current supply circuit are associated with each other, and each connected in series betweeen a low supply voltage and high supply voltage. The input side of the ROM can be kept at a stabilized low potential, and information stored in a selected memory element can be read out based on the value of an inflow current into the read and sense circuit.