Circuitry for complementing binary numbers

Abstract

Circuitry for forming the twos complement or ones complement of M-bit binary numbers is described. The circuitry includes M stages each of which contains an exclusive NOR gate. A first input terminal of the exclusive NOR gate is coupled to receive one bit of the input value and a second input terminal is coupled to receive the carry output signal from the previous stage. A logic one or logic zero is applied to the second input terminal of the stage which processes the least significant bit of the binary word if the circuitry is to provide a twos complement or ones complement value respectively. The carry output signal for each stage is generated by ANDing a logically inverted version of the input bit signal with the carry input signal applied to the stage. An application of the complementing circuitry in an absolute value circuit is also described. In this application, the carry input signal of each stage is ORed with a logically inverted version of the sign bit of the input value and the result is applied to the second input terminal of the explained NOR gate. This circuitry complements only negative values, passing positive values unchanged.