The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 1987

Filed:

May. 19, 1986
Applicant:
Inventors:

Yoshito Nishimichi, Moriguchi, JP;

Masaru Uya, Hirakata, JP;

Katsuyuki Kaneko, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307243 ; 307279 ; 307443 ; 307473 ; 307585 ;
Abstract

An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.


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Nishimichi, Yoshito. (1987). Integrated circuit having latch circuit with multiplexer selection (U.S. Patent No. 4709173). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4709173

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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