Data processing circuit for digital audio system

Abstract

There is provided a data processing circuit for processing symbol data read from a disc of a digital audio system such as a DAD player. Each of the symbol data read from the disc is first stored into a buffer register and then transferred therefrom to a symbol memory in accordance with internal pulse signals, and the number of the pulse signals generated during a period required to process one frame of symbol data is greater than that of symbol data contained in one frame of symbol data. An address data for addressing a desired area of the symbol memory is formed by adding a reference address data generated by counting the internal frame synchronization signals to a relative address data generated by adding together a specific pair of addressing data read out from an address memory, the address memory storing a plurality of groups of addressing data to be used in accordance with each mode of operation of this circuit. When the symbol data is written into the symbol memory, the reference address data is modified by adding an output of an up/down-counter to compensate for jitters of the symbol data, the up/down-counter counting frame synchronization signals discriminated from the data read from the disc in one of upward and downward directions and counting the internal frame synchronization signals in the other of upward and downward directions.