The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 1987
Filed:
Sep. 07, 1984
Steve Dumbovic, Elmhurst, IL (US);
Mark A Dempsky, Villa Park, IL (US);
Illinois Tool Works Inc., Chicago, IL (US);
Abstract
A method for effecting full duplex communications through a plurality of ports of a processing apparatus having one timer. Each output and input signal is expressed as a plurality of bit time intervals. The timer is operated to establish cycles of duration equal to the bit time interval with each of the cycles being divided into sub-bits; designating one of the sub-bits within each of the cycles as a transmitting sub-bit and, upon commencement of the transmitting sub-bit, latching the output pins of appropriate ports at a signal level indicating an output signal bit for transmission at such ports and, upon completion of that latching, interrogating all of the ports for presence of an input signal; upon commencement of sub-bits other than a transmitting sub-bit, interrogating all of the ports for presence of input signals; designating sub-bits of a first cycle during which presence of an input signal is detected as initial sub-bits and identifying sub-bits immediately succeeding initial sub-bits as confirming sub-bits on a port-by-port basis; recognizing input signals detected during confirming sub-bits as true input signals and tagging ports at which true input signals are detected as true input ports; after such tagging, effecting selective interrogation of true input ports in subsequent cycles during sub-bits appearing in a sequential order corresponding to the confirming sub-bits in the first cycle, which selective interrogation of each of the true input ports continues until the input signal at respective true input ports ceases.