The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1987

Filed:

Feb. 20, 1986
Applicant:
Inventors:

Kazuo Terada, Tokyo, JP;

Susumu Kurosawa, Tokyo, JP;

Shunichi Suzuki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
357 235 ; 357 24 ; 357 14 ; 357 236 ; 357 42 ; 357 46 ; 357 2311 ; 357 2314 ; 365150 ; 365149 ; 365184 ;
Abstract

A semiconductor memory device has a semiconductor substrate with a first semiconductor region of one conductivity type in the substrate. A second semiconductor region of the opposite conductivity type is formed in the first semiconductor region. A third semiconductor region of the opposite conductivity type is arranged to be in contact with the first semiconductor region. A fourth semiconductor region of the one conductivity type is formed in the third semiconductor region. A fifth semiconductor region of the one conductivity type, within the semiconductor substrate, has a concentration which is higher than the impurity concentration of the first semiconductor region and is provided under the third semiconductor region. A continuous gate electrode is provided via a gate insulating layer formed on the surface of the first semiconductor region and on the surface of the third semiconductor region. The first, second and third semiconductor regions and the gate electrode form a first insulated-gate field effect transistor. The second, third and fourth semiconductor regions and the gate electrode serving as a second insulated-gate field effect transistor.


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