Solid state dc rate of rise controlled switch

Abstract

A solid state dc switch for switching power from the positive terminal of a ground referenced dc voltage source to the terminal of a ground referenced load. The solid state switch has a divide-by-two circuit means responsive to a clock signal and to a control signal first state for providing first and second symmetrical output signals at a frequency of one-half the frequency of said clock frequency. It also has a transformer drive and rectifier means for providing an isolated dc signal. An isolated switching means is included which is responsive to the high state of an isolated dc signal, having a transistor switch having a collector, an emitter and a base, the collector being coupled to a positive terminal of a ground referenced voltage source. The emitter is coupled to the return of the ground referenced load. The base is coupled to an isolated dc signal. The switching means is responsive to the change of state of the isolated dc signal from a low to a high state for limiting the rate of rise of voltage on a load to a predetermined limit subsequent to a change of state. The switching means is also responsive to the change of state of an isolated dc signal from a high state to a low state for limiting the rate of fall of voltage on a load subsequent to a change of state of an isolated dc signal from a high state to a low state.