The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 1987

Filed:

Jul. 08, 1985
Applicant:
Inventors:

Deepak Mahulikar, Meriden, CT (US);

Satyam C Cherukuri, West Haven, CT (US);

Assignee:

Olin Corporation, New Haven, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 74 ; 357 73 ; 357 67 ;
Abstract

A graded seal assembly adapted for hermetically sealing a semiconductor package is disclosed. First and second members having first and second coefficients of thermal expansion respectively are provided. A leadframe is disposed between the first and second members. A first sealing glass is bonded to opposite surfaces of the leadframe and is disposed between the leadframe and the first member for sealing the leadframe to the first member. The second sealing glass is bonded to the second member. The second sealing glass has a third CTE which has a mismatch of less than about 5.times.10.sup.-7 in/in/.degree.C. with said second member. A graded interface zone having stratified layers fuses the first and second sealing glasses. Each of the layers in the zone has a coefficient of thermal expansion which is mismatched less than about 5.times.10.sup.-7 in/in/.degree.C. with an adjacent layer to absorb thermal stress formed by exposure of the semiconductor package to thermal cycling.


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