The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1987

Filed:

Mar. 07, 1986
Applicant:
Inventors:

William F Herzog, Gilroy, CA (US);

William E Nichols, San Jose, CA (US);

Assignee:

Apert-Herzog Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358160 ; 358 / ; 358111 ;
Abstract

A memory stores and repetitively plays back for display an continuously repeating, consecutive sequence of picture frames derived from a source. The memory includes an input for receiving digitized picture element values in a serial bit stream and for framing the stream into consecutive constant length pluralities of digital picture element words. A read/write solid state semiconductor frame memory array is arranged as a ring for storing and playing back a predetermined number of the consecutive video picture image frames. An output receives constant length pluralities of digital picture element words read from the memory array and converts them into an analog picture signal for display. A read/write memory array control controls writing to and reading from the frame memory array so that a selected segment of consecutive video picture frames may be repeatedly played back without interruption at a real time image display rate. The memory read/write memory array control may include a write protect circuit for enabling an operator to single step through a series of consecutive frames written in the array, the write protect circuit for generating and storing at least one write protection value for write protecting at least one of the frames so written. The read/write memory array control further may include a circuit for skipping said at least one write protected frame during subsequent write operations of the memory array and may also include a clear circuit for clearing the write protection value or values.


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