Logic network for d/a conversion

Abstract

A digital-to-analog conversion circuitry is provided wherein a switching network is adapted to couple, or decouple, a selected one, or ones, of a plurality of identical current sources to, or from, an output bus selectively in accordance with the digital word being converted to produce an output current through an output bus having a level related to such digital word. The switching network includes: a logic network for selectively combining the plurality of bits of the digital word to produce a plurality of control signals, at least one thereof being related to a plurality of the bits of the digital word; and, a plurality of switching transistors, each one thereof having: a control (or base) electrode coupled to a corresponding one of the plurality of control signals; a first (or emitter) electrode coupled to a corresponding one of the plurality of identical current sources; and a second (or collector) electrode coupled to the output bus, such current source being coupled to, or decoupled from, such output bus selectively in accordance with the control signal fed to the control electrode of the transistor coupled to such current source, the logic network produces the plurality of control signals with substantially equal switching level variations. With such arrangement, the level of current produced by each current source and its contribution to the total output current are independent of the digital word being coverted and the level of current contributing to the total current flow through the output bus is also independent of the digital word being converted. Further, the switching time of the switching transistors is also independent of the digital word being converted.