The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 1987
Filed:
Feb. 03, 1986
Akio Nakagawa, Hiratsuka, JP;
Hiromichi Ohashi, Yokohama, JP;
Tsuneo Ogura, Kamakura, JP;
Masaru Shimbo, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200.degree. C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.