The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 1987
Filed:
May. 10, 1985
Srikumar R Chandran, San Jose, CA (US);
Mark S Walker, San Jose, CA (US);
Tandem Computers Incorporated, Cupertino, CA (US);
Abstract
A digital logic circuit and method for synchronizing the leading edges skewed true-complement signal pair. The circuit is comprised of two similar, interconnected circuit halves, each of which includes three D flip-flop stages. The outputs from the second D flip-flop stages from the two circuit halves are applied to the two inputs of two identical logic gates, such that the signal pair is synchronously transmitted to a pair of output gates through a third D flip-flop stage in each circuit half. The second D flip-flop stages also prevent metastable states from reaching the synchronizer output. Metastable states may result if the input setup time is violated for the first D flip-flop stages. The third D flip-flop stage in each circuit half also eliminates any signal irregularities generated in the logic circuitry from appearing on the synchronizer output lines. The circuit is self-checking in that any single fault in the input signals or in the synchronizer circuit itself will result in the synchronizer output pair not having a true complement relationship.