The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 1987

Filed:

Mar. 01, 1985
Applicant:
Inventor:

Ravindra K Nair, Peekskill, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
364488 ; 364491 ;
Abstract

A method of generating the layout of CMOS cells from a high-level functional description of the cells, as well as generating the particular details of the CMOS device. In particular, the image of the chip is formed having the polysilicon gates of the transistors on the n-side vertically aligned with those of the p-side vertically aligned with those of the p-side to minimize the wiring effort. The interconnections between the source and drains are orthogonal to the gates, and run along one layer of metal.


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