The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 1987

Filed:

Oct. 20, 1986
Applicant:
Inventor:

Graham S Tubbs, Tempe, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307480 ; 307443 ; 307453 ; 307468 ; 307481 ; 365233 ;
Abstract

A multi-level logic circuit includes a first plurality of logic circuits that are connected in a cascade arrangement. A second plurality of dummy logic circuits also connected in casacade arrangement are used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source provides a precharged signal to the first plurality of logic circuits and the second plurality of dummy logic circuits and an evaluation circuit is used to combine the clock signal with an output signal from the dummy logic signal to obtain an evaluation signal for evaluating the logic states of the first plurality of logic circuits.


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Tubbs, Graham. (1987). Dummy load controlled multilevel logic single clock logic circuit (U.S. Patent No. 4700088). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4700088

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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