The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1987
Filed:
Jul. 01, 1985
Motorola, Inc., Schaumburg, IL (US);
Abstract
A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders. The static RAM has an architecture characterized by the memory having a top side, a bottom side, a left side, and a right side; the rows of sub-arrays running from left to right, and sequentially numbered from left to right with the first column of sub-arrays being nearest the top side; the columns of sub-arrays running from top to bottom, and sequentially numbered from top to bottom with the first row sub-arrays being nearest the left side; and the plurality of sense amplifiers being interposed in the rows of sub-arrays and located between the columns of sub-arrays.