The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 1987

Filed:

Apr. 11, 1986
Applicant:
Inventors:

Tatsuya Kubota, Kanagawa, JP;

Kenji Takanashi, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358140 ; 358105 ; 358160 ;
Abstract

A video signal control circuit having a memory, a write address generator for generating a write address data supplied to the memory, by which an input digital video signal is written in the memory at the address represented by the write address data, a read address generator for generating a read address data supplied to the memory, by which a controlled digital video signal is read out from the memory at the address represented by the read address data, an address comparator for comparing the write and read address data and for generating a compared output pulse, a timing pulse generator for generating first and second timing pulses, each of which has a predetermined pulse duration, a still picture detector supplied with the input digital video signal and for detecting whether the input digital video signal represents a still picture or not, a write address controller supplied with the compared output pulse, the first timing pulse and the output of the still picture detector and for controlling the write address generator when the pulse duration of the compared output pulse is shorter than that of said first timing pulse and the still picture detector detects that the input digital video signal represents a still picture, and a read address controller supplied with the compared output pulse, the second timing pulse and the output of the still picture detector and for controlling the read address generator when the pulse duration of the compared output pulse is shorter than that of the second timing pulse and the still picture detector means detects that the input digital video signal represents a still picture.


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