The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1987
Filed:
Feb. 11, 1986
Tadahiro Saito, Kawasaki, JP;
Kunihiko Gotoh, Kunitachi, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor integrated circuit formed on a chip comprises an internal circuit and an oscillating circuit, the latter generating a fundamental clock signal and a frequency divided version thereof, for operating the former in a non-testing mode of operation. A pair of first and second external connection terminals is formed on the chip and respectively connected to the input and the output of the oscillating circuit. An external oscillator is selectively connected between the pair of terminals for operating the internal circuit in a non-testing mode. A reset signal input of the internal circuit is connected to a reset external connection terminal for receiving an externally applied reset signal which resets the internal circuit. A switching circuit is responsive to a predetermined level of each of respective input signals externally applied to the reset terminal and the second external terminal for rendering the oscillating circuit inoperative and for switching the switching circuit from a first position which supplies the frequency divided fundamental clock signal to the internal circuit in the non-testing mode, to a second position connected in common with the output of the oscillating circuit to the second external terminal for supplying a testing clock signal, selectively applied to the second external terminal in the testing mode, to the internal circuit.