The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1987
Filed:
Nov. 28, 1983
Noboru Masuda, Kokubunji, JP;
Michio Asano, Kokubunji, JP;
Takehisa Hayashi, Kokubunji, JP;
Hirotoshi Tanaka, Hachioji, JP;
Akira Masaki, Tokyo, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
An input buffer for a semiconductor circuit is provided with a source follower circuit composed of a first FET whose gate electrode has an input connected thereto, and a second FET of the same conductivity type as that of the first FET, whose drain electrode is connected to a source electrode of the first FET directly or through at least one level-shifting diode and whose gate electrode is supplied with a control voltage. The input buffer also includes a FET inverter circuit connected to the drain electrode of the second FET directly or through at least one level-shifting diode. An output signal for the input buffer is derived from the FET inverter circuit. A particular advantage of the present invention is that it permits the input buffer to switch its output from one level to another in response to input signals falling within a predetermined voltage range regardless of logic threshold level fluctuations in the FETs and fluctuations in supply voltages coupled to the input buffer.