Charge balance voltage-to-frequency converter utilizing cmos circuitry

Abstract

A charge balance voltage-to-frequency converter utilizes CMOS circuitry to provide a digital pulse output proportional to an analog input signal. The converter approaches a desired charge balance by cycling between a charging and a discharging state. A clock signal provided by a stable oscillator is applied to a clock input of a CMOS D-type flip-flop. The analog input signal effectively is fed to a non-inverting input of an integrating amplifier. The output of the integrating amplifier is fed to the D input of the flip-flop, which input has a threshold level. The Q output of the flip-flop is connected via a voltage divider to an inverting input of the integrating amplifier. This configuration eliminates the need for a dual polarity power supply. When the output of the integrating amplifier rises above the threshold level of the D input, on the next rising edge of the clock signal, the flip-flop sends feedback pulses to the inverting input, thus beginning the discharge state. Each feedback pulse causes the integrating amplifier to discharge a predetermined amount. When the output of the integrating amplifier falls below the D input threshold level, feedback pulses are inhibited, and the charging state begins again. The output pulses from the flip-flop, when accumulated over a period of time, represent the charge required to balance the charge provided by the input signal. The feedback pulses are summed by an accumulator to provide an indication of the converter input.