System for performing virtual look-ahead memory operations

Abstract

A system is disclosed which reduces the cycle time required for performing virtual look-ahead memory operations in computer systems employing random access memory and paging. In a preferred embodiment of the invention, a processor (CPU) outputs a desired virtual address to an address translation unit (ATU) and to a memory output control unit (MOC) and also outputs processor signals to the ATU and to a memory state generator (MSG). The virtual address is comprised of a first real address and a second virtual address. During a first cycle this first real address is gated through a memory output control unit (MOC) to cause an addressable memory, which is arranged to store data in a page format, to commence memory addressing prior to the completion of translation by the ATU. During the first cycle the ATU translates the second virtual address into second and third real address portions. During a second cycle a decoder decodes the third real address portion to develop memory operation signals which determine which one of a plurality of virtual memory operations is to be performed. The MSG is responsive to these memory operation signals and to the processor signals for developing a set of state signals which determines the type of memory operation that is to be performed, as well as the number of cycles required to perform that operation. Under the control of the set of state signals from the MSG, a memory timing control circuit (MTC) controls the MOC to develop memory control signals and to gate the second real address from the ATU and the memory control signals to the addressable memory to access the data in a reduced cycle time for the desired virtual memory operation. The system has the capability of also performing a plurality of real memory operations.