Circuit arrangement comprising a matrix-shaped memory arrangement for

Abstract

A circuit arrangement comprises a matrix-shaped memory for variably adjustable delay of digital signals, whereby trigger elements in the form of two inverters fed back to one another are provided as storage elements, one of the two nodes thereof being connectible to a write bit line by way of a switching transistor controllable from a write word line and the other being connectible to a read bit line via a switching transistor controllable from a read word line. A row selector is clocked by the input data clock and is continuously settable and resettable at any time, the row selector comprising two signal outputs per selection stage which are offset in phase relative to one another, these respectively selecting one of the write word lines or read word lines which are provided per row of the matrix-shaped memory. Two separate bit lines, namely a write bit line and a read bit line are provided per column, these being respectively interconnected to all memory cells of a column. A disconnectible storage amplifier is provided per column, the input thereof being connected to the read bit line of the column assigned thereto and the output thereof being connected to the write bit line of the column following thereafter and serving as a data output. A data input for the data signals to be delayed is connected to the write bit line of the first column.