The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 1987

Filed:

Aug. 23, 1984
Applicant:
Inventor:

Tsuneo Kinoshita, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract

A 16-bit microprocessor (.mu.P) system uses memory access data consisting of: a status field for memory control data including a specific bit; a segment field; and a 16-bit address field. In a .mu.P, an instruction under execution comprises an .alpha. instruction in an operand fetch cycle, an index-modified value of a 16-bit lower logical address is set in an MAR, and a sum of an 8-bit upper logical address word and a carry flag is set in an SGB (Segment Register B). The .mu.P sets the memory control data having the specific bit of a first logic level in an MCS (Memory Control Status Register), and thereafter generates the memory access data. In this case, the content of the SGB is used for the segment field in place of the segment number stored in an SGA (Segment Register A). When the specific bit of the status field of the memory access data from the .mu.P, is set at a second logic level, a segment/page table is accessed by the segment field and part (page number) of the address field, thereby generating the page data. A basic address space is accessed by a physical address obtained by linking the page data and the remaining data (displacement) of the address field. On the other hand, when the specific bit is set at the first logic value, a expanded address space is accessed by a physical address obtained by linking the segment field and the address field.


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