Redundant synchronous clock system

Abstract

A synchronous clock circuit is provided on each module of an electronic digital system formed of a plurality of modules. Each clock circuit has two control pins which are used by control logic to determine whether or not the clock on a particular module is disabled, is operating as the master clock for the system, or is providing a backup function for the master clock. The common clock line is supplied through a buffer to the components on the module which require clocking. Logic circuitry on the backup clock mode insures the backup clock is in a ready condition in case there should be either failure of the master clock oscillator or if the master clock module is removed from the unit. All of the clock circuits of the different modules may be constructed in an identical manner, with the control of the function of the circuitry being provided simply by control of the logic level on the two terminals. A clock detecting time-out circuit is provided on each of the modules, which has a timing period which is slightly longer than the clock period. If the master clock fails to produce a clock pulse at the time that it should, the clock detect timing circuit, which is coupled to the buffer of the backup module, will sense that a failure has occurred and will control the turn-on of the clock circuit for the backup module.