Method and apparatus for reduction of sinusoidal phase jitter in a high

Abstract

An apparatus for cancellation of sinusoidal varying phase jitter in a data modem is implemented in firmware using microprocessor technology. An estimate of the frequency and phase of the phase jitter is computed in a first stage. Substantially independently, an estimate of the amplitude of the phase jitter is computed in another stage. These estimates are combined to form a composite estimate of the phase jitter which is utilized to cancel out the sinusoidal phase jitter in the demodulator. Digital phase locked loop technology (DPLL) is utilized to lock onto the phase jitter components. The capture range of the phase locked loop is dynamically altered during a training sequence to allow for capturing a wide range of jitter frequencies. During the training sequence the damping factor of the loop is gradually altered thereby substantially reducing the capture range and response time of the loop once jitter acquisition has occurred. This results in enhanced noise performance while still retaining the capability of locking to a wide range of jitter frequencies. Quantization of the error signal is utilized to compute estimates of the frequencies and phase of the jitter signal so that continuous updating occurs virtualy without regard for the amplitude or change in amplitude of the jitter signal.