The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 1987
Filed:
Dec. 03, 1986
Yoshiki Shimauchi, Kawasaki, JP;
Katsuji Hirochi, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the base thereof, a first NPN-type transistor whose base is connected to the emitters of the PNP-type transistors, and an output buffer circuit. The output buffer circuit includes a second NPN-type transistor, which is controlled by the signal at the emitter of the first NPN-type transistor and outputs electric charges from an output terminal, and a third NPN-type transistor, which is controlled by the signal at the collector of the first NPN-type transistor and which is connected in series with the second NPN-type transistor so as to supply a charging current to the output terminal.