Apparatus and method for determining true data in a digital data stream

Abstract

A method and circuit for estimating true data from distorted digital data signals which may have become degraded due to noise, in which signals are clocked into a shift register at a frequency rate higher than the data rate, for example eight times the data rate. The n outputs of the shift register stages are coupled to respective inputs of a majority logic circuit which has (n+1) inputs. A latching circuit clocked in antiphase to the clocking of the shift register is coupled to an output of the majority logic circuit. The output of the latching circuit is fed back to the (n+1)th input of the majority logic circuit.