The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 1987

Filed:

Aug. 02, 1984
Applicant:
Inventors:

Reiner Lassmann, Munich, DE;

Albert Krupp, Munich, DE;

Peter Fazekas, Munich, DE;

Assignee:

Siemens Aktiengesellschaft, Berlin and Munich, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ; G01R / ; G01R / ;
U.S. Cl.
CPC ...
324 / ; 3241 / ; 371 25 ;
Abstract

Time-critical events are localized within a clocked electronic circuit without requiring cyclical operation By way of measuring at the outputs of the circuit, the limit frequency of the circuit is identified. A test pattern sequence is then applied to this circuit. The number n of that test pattern at which errors are perceived at the outputs is identified, in particular with a clock frequency higher than the identified limit frequency of the circuit. The test patterns having the numbers n-m are applied to the circuit with a clock frequency greater than the identified limit frequency of the circuit and the remaining n test patterns are applied to the circuit with a clock frequency lower than the identified limit frequency of the circuit, being applied thereto in succession step-by-step with m=1,2,3 . . . in at least one run of n test patterns. A check is carried out after every run of a test pattern sequence of n test patterns as to whether an error still exist at the output until an error can no longer be documented at the output and a determination is thus made with respect to which test pattern having the number n-m the error is generated within the -circuit. An error tracking technique is carried out in order to localize the cause of error within the electronic circuit.


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